An integrated circuit (“IC”) is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
Design engineers design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. IC design layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC.
To create the design layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts.
Fabrication foundries (“fabs”) manufacture ICs based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (photo mask) are imaged and defined onto a photosensitive layer coating a substrate. To fabricate an IC, photo masks are created using the IC design layout as a template. The photo masks contain the various geometries (i.e., features) of the IC design layout. The various geometries contained on the photo masks correspond to the various base physical IC elements which comprise functional circuit components such as transistors, interconnect wiring, via pads, as well as other elements which are not functional circuit elements but are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photo masks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
As circuit complexity continues to increase and transistor designs become more advanced and ever smaller in size, advances in photolithographic processes are being pursued to enable the large scale, low cost manufacturing of such circuits. However, constraining factors in traditional photolithographic processes limit the effectiveness of current photolithographic processes. Some such constraining factors include pitch and width constraints associated with the lights/optics used within photolithographic processing systems.
A pitch specifies a sum of the width of a feature and the space on one side of the feature separating that feature from a neighboring feature. Depending on the photolithographic process at issue, factors such as optics and wavelengths of light or radiation restrict how small the pitch may be made before features can no longer be reliably printed to a wafer or mask. As such, the smallest size of any features that can be created on a wafer is severely limited by the pitch.
FIGS. 1 and 2 illustrate typical pitch constraints imposed by a photolithographic process. In FIG. 1, an orthogonal pitch 110 acts to constrain the spacing between printable features 120 and 130 of a design layout, while in FIG. 2 a diagonal pitch 210 acts to constrain the spacing between features 220 and 230. While other photolithographic process factors such as the threshold 140 can be used to narrow the width 150 of the features 120 and 130, such adjustments do not result in increased feature density without adjustments to the pitch 110 or 210. As a result, increasing feature densities beyond a certain threshold is infeasible via a pitch constrained single exposure process.
Certain reticle enhancement techniques (RET) allow for photolithographic processes to extend beyond some of the various photolithographic manufacturing constraints such as the width constraint. Some common techniques include: using optical proximity correction (OPC) to distort photo mask shapes to compensate for image errors resulting from diffraction or process effects that cause pattern inaccuracies, using off-axis illumination (OAI) for optimizing the angle of illumination for a particular pitch, using alternating phase shift masks (PSM) for improving lithographic resolution by introducing a particular phase shift between adjacent patterns or features on a photo mask, and using scatter bars to place narrow lines or spaces adjacent to a feature in order to make a relatively isolated line behave more like a dense line.
However, these and other techniques are limited both by cost and effectiveness. Moreover, the reticle enhancement techniques described above do not overcome the pitch constraints of FIG. 1. To overcome the pitch constraints, some fabrication processes have implemented a multiple exposure photolithographic process as illustrated in FIG. 3.
In FIG. 3, a design layout 305 specifies three features 310-330 that are pitch constrained and therefore cannot be photolithographically printed with a conventional single exposure process. Analysis of the characteristics (e.g., the pitch) of the available photolithographic process and of the design layout 305 results in the decomposition of the design layout 305 into a first exposure 340 for printing features 310 and 330 and a second exposure 350 for printing feature 320. As such, the features 310 and 330 are assigned to a first photo mask for printing during the first exposure 340 and feature 320 is assigned to a second photo mask for printing during the second exposure 350. Several examples of such processes are provided in U.S. patent application Ser. No. 11/405,029 entitled “Method and System for Printing Lithographic Images with Multiple Exposures”, filed on Apr. 14, 2006, issued as U.S. Pat. No. 7,310,797.
Existing decomposition tools for performing layout decomposition are often rule based. Such tools are therefore applicable only to patterns for which a pre-programmed or known decomposition solution exists within a library. These tools are effective for decomposing simple designs with regular repeating patterns such as gradings including lines and spaces. However, design layouts with more sophisticated designs (e.g., logic designs and microprocessor designs containing complex patterns and shapes with bends and jogs) cannot be processed using these existing decomposition tools as solutions do not exist for the unique patterns appearing within such design layouts. Instead, layout designers would be notified of the patterns for which a known solution does not exist. The layout designers would then be prompted to manually produce a decomposition solution for these patterns.
Moreover, existing decomposition tools are inefficient in the manner by which they perform decomposition analysis. Repeated polygonal patterns within a single design layout are each independently analyzed and a solution is provided for each instance as if each instance is the first such instance. The prior art fails to build upon and leverage the knowledge that could be gleaned from the earlier passes through the layout and the newly entered decomposition solutions received from the design engineers. For example, for a pattern with an unknown decomposition solution, the layout designer would be prompted to produce a decomposition solution. The solution received from the layout designer would be integrated into the design but would not be integrated into the library of existing solutions where the solution could be reused for a similar pattern subsequently encountered during decomposition analysis.
Furthermore, the effectiveness of prior art decomposition processes is further limited as potential photolithographic printing errors and other errors remain undetected. For instance, a decomposition of a design layout may logically appear to be error free. However, various photolithographic errors such as pinching, necking, and various other printing errors may be produced by the photolithographic process after the logical decomposition is physically printed onto a wafer. Such errors often lead to opens between otherwise connected circuits and shorts between otherwise unrelated circuits in the physical implementation. Without proper simulation of the photolithographic printing, such errors remain undetected.
Therefore, there is a need to efficiently and effectively decompose an entire layout or section of a layout and to simulate the decomposed layout or section of the layout to account for potential photolithographic printing errors. There is a need for such operations to reuse existing known solutions and to provide solutions for unknown patterns within a design layout by computing new solutions through the various simulations that validate a give solution. There is further a need for an adaptable system and method that stores and reuses newly computed decomposition solutions so that such decomposition solutions are not continually recomputed at each instance a pattern is encountered within a design layout.